1. Field of the Invention
The present invention relates to phase-locked loops (PLL) in general, and, more particularly, to PLL having circuits which optimize the acquisition time of said loops and control the tracking characteristics.
2. Prior Art
The use of phase-locked loops (PLLs) in the field of electromechanical control, data acquisition, etc. is well known in the prior art. A typical PLL consists of a phase detector, a low-pass filter and a voltage-controlled oscillator (VCO). The enumerated elements are coupled to form a closed-loop system. The phase detector measures differences in phase between an incoming signal and a feedback signal from the VCO. Any detected differences generate an error signal which is filtered and is supplied to the VCO. The VCO utilizes the error signal so as to minimize the frequency difference between the feedback signal and the incoming signal.
Many applications require that the PLL have a tight frequency control, short acquisition or lock time, and relatively wide lock frequency range. Unfortunately, these requirements are mutually exclusive. Therefore, a design which tends to achieve one of the above requirements tends to adversely affect the others.
U.S. Pat. No. 4,007,429 describes a phase-locked loop with a switched low-pass filter. The switched low-pass filter has two different bandwidths. One of the bandwidths has a wide frequency response for use during acquisition period. The other bandwidth has a relatively narrow frequency response and is used during normal tracking for tight control of the voltage-controlled oscillator. A loss-of-lock detector controls the particular filter bandwidth state by causing certain filter components to be switched in and out according to the presence or absence of phase-lock condition.